The present invention relates to a frequency divider, and particularly to a dynamic frequency divider comprising differential circuits. The present invention also relates to a phase lock oscillator using such a frequency divider. Further, the present invention relates to a flip-flop circuit obtained by improving the frequency divider.
A dynamic frequency divider, using differential circuits, is known as a frequency divider suitable for a high-speed operation. FIG. 1 shows a conventional dynamic frequency divider, wherein a ring oscillator structure is made of two basic gates, each having a pair of emitter-coupled differential transistors, which constitute a differential circuit, and an emitter follower which receives outputs from the collectors of the transistors.
More specifically, a basic gate 1 of a first stage (first basic gate 1) comprises a first pair of emitter-coupled differential transistors Q1 and Q2, to which resistors R1 and R2 serving as collector loads are connected, and an emitter follower comprised of transistors Q3 and Q4 which receive collector outputs of the transistors Q1 and Q2. Similarly, a basic gate 2 of a second stage (second basic gate 2) comprises a second pair of emitter-coupled differential transistors Q5 and Q6, to which resistors R3 and R4 serving as collector loads are connected, and an emitter follower comprised of transistors Q7 and Q8 which receive collector outputs of the transistors Q5 and Q6.
Emitter outputs of the transistors Q7 and Q8 constituting the emitter follower of the second basic gate 2 are fed back to the bases of the emitter-coupled differential transistors Q1 and Q2 of the first basic gate 1, so that the phase of a signal is inverted in one cycle.
The common emitter of the emitter-coupled differential transistors Q1 and Q2 of the first stage and the common emitter of the emitter-coupled differential transistors Q5 and Q6 are respectively connected to the collectors of a third pair of emitter-coupled differential transistors Q9 and Q10. The common emitter of the emitter-coupled differential transistors Q9 and Q10 is connected to a current source CS1. The emitters of the transistors Q3, Q4, Q7 and Q8 constituting the emitter followers are individually connected to current sources CS3, CS4, CS7 and CS8.
Differential input signals CK and /CK are input to the bases of the third pair of emitter-coupled differential transistors Q9 and Q10. Frequency-divided output signals are obtained from outputs OUT and /OUT of the emitter follower (emitter outputs of the transistors Q7 and Q8) of the second basic gate 2.
FIG. 2 shows a characteristic of an input signal power sensitivity with respect to a division frequency (a frequency of an input signal to be divided) in the conventional dynamic frequency divider. Unlike the normal frequency divider, the dynamic frequency divider performs self-excited oscillation at a specific frequency, i.e., free-running frequency f.sub.freerun, even if an input signal power is not input. As shown in FIG. 2, the input signal power sensitivity is high at the free-running frequency f.sub.freerun. At the other frequencies, a high input signal power is required. In other words, the input signal power sensitivity is low in a frequency range other than the free-running frequency.
Therefore, to extend the range of the use frequency of the frequency divider, it is effective to vary the free-running frequency. For this reason, the conventional art employs a method of varying the free-running frequency by changing the current value of the current source CS1 shown in FIG. 1. According to this method, however, the amplitude of an output signal is changed depending on the current value of the current source CS1. In other words, the method is disadvantageous in that the amplitude of an output signal is changed depending on the division frequency. Thus, the method is not suitable for practical use.
Moreover, the maximum division frequency of the conventional dynamic frequency divider is 1/2 .tau.d, which is substantially determined by a delay time .tau.d per basic gate. Therefore, to increase the maximum division frequency, i.e., to realize a high-speed operation, it is important to reduce the delay time .tau.d. The delay time .tau.d is the sum of the minimum switching time of the pair of emitter-coupled differential transistors and the delay time of the emitter follower in one basic gate. Since these values are substantially determined by the performance of the transistors, reduction in the delay time .tau.d is inevitably limited.
As described above, the conventional dynamic frequency divider has the following drawbacks. First, if the free-running frequency is varied to extend the range of the use frequency, the amplitude of an output signal is changed depending on the frequency. Secondly, reduction in the delay time is limited, since the maximum division frequency is substantially determined by a delay time per basic gate, and the delay time is the sum of the switching time of the pair of emitter-coupled differential transistors and the delay time of the emitter follower in the basic gate and determined by the performance of the transistors.